SPEEDY: Single-Step Reinforcement Learning for Efficient Analog Circuit Sizing Optimization

Analog circuit sizing is usually posed as a sequential decision problem, which makes it expensive: every step costs a simulation. SPEEDY learns to propose a sizing in a single step instead, cutting runtime more than 8× against a 100-step DDPG baseline and more than 2× against Bayesian optimization, while raising the OTA pass rate to 10/10 where DDPG reaches 0/10. A design-range refinement method shrinks the search volume by roughly eleven orders of magnitude on a 25-specification LDO.

Under review